The present invention relates generally to semiconductor devices and more particularly to phase change material memory cells and methods for fabricating phase change material memory cells.
Phase change materials are alloys in which the structural states of the material may be electrically switched between generally amorphous and generally crystalline local order in a controlled fashion. In these materials, the crystalline state is known to have a lower resistivity than the amorphous state. Such materials are sometimes used to form memory storage devices, for example, where the structural state of the material is indicative of data or other information stored in a particular cell. In some such phase change memory cells, binary data may be stored where the low resistivity crystalline state is used to indicate a binary xe2x80x9c0xe2x80x9d and the higher resistivity amorphous state indicates a binary xe2x80x9c1xe2x80x9d or vice versa. The nature of phase change materials also allows controlled setting or xe2x80x9cprogrammingxe2x80x9d of the material state to one or more intermediate states or local orders between the completely amorphous and completely crystalline states. This characteristic allows use of these materials in other (e.g., non-binary) memories. In this regard, the electrical switching of such materials need not take place between completely amorphous and completely crystalline states. Rather, the electrical switching may be performed in incremental steps so as to provide a xe2x80x9cgray scalexe2x80x9d represented by a multiplicity of conditions of local order along a range between the completely amorphous and the completely crystalline states.
Another feature of phase change materials is the ability to program memory cells without first having to erase the cell. For instance, in a binary phase change material memory cell, the cell may be programmed directly to either a xe2x80x9c1xe2x80x9d or to a xe2x80x9c0xe2x80x9d, regardless of the previous state. In programming memory cells constructed of phase change material, an electrical current of sufficient magnitude is passed through the material, usually in the form of a pulse of limited time duration and controlled magnitude. The programming current causes thermal and/or electrically induced structural changes in the material in order to set the structure to a given state (e.g., completely amorphous, completely crystalline, or an intermediate state). As programming current flows, the phase change material melts into an amorphous state, regardless of the initial state. Where a relatively short duration current pulse is applied, the material cools quickly, and remains in a generally amorphous state. This effectively sets or xe2x80x9cprogramsxe2x80x9d the cell material to a electrical high resistivity (e.g., a binary xe2x80x9c1xe2x80x9d, for example).
Alternatively, where a longer duration pulse is used, the material cools more slowly, and transitions into a generally crystalline state having a relatively low resistivity (e.g., used to indicate a binary xe2x80x9c0xe2x80x9d). By controlling the pulse duration and the current magnitude, therefore, the memory cell having such phase change material may be programmed or set to either an amorphous or crystalline state in order to function as a binary data store. In this regard, the duration and current amplitude may further be controlled or varied so as to achieve any desired final state (e.g., after cooling), by which non-binary information storage may be achieved. The cell may thereafter be read by applying a current pulse of lower magnitude (e.g., low enough to prevent material melting), by which the resistivity of the cell material (e.g., and hence the value of the data stored or programmed therein) can be ascertained.
A conventional phase change material memory cell 10 is illustrated in FIGS. 1a and 1b, having a volume of phase change material 12 of the type described above, which goes through a state change depending upon a current 14 passing therethrough. The cell 10 is connected to a MOSFET type transistor 20 formed in a semiconductor memory device 2 for programming and reading of the cell 10. The phase change material 12 is situated between an overlying conductive contact 16 and an underlying resistive structure or plug 18 laterally surrounded by a high resistivity material 30. The plug 18 and the material 30 are formed over another conductive contact 32, which in turn, is connected to a source/drain structure 22 of the transistor 20 by a conductive via structure 34. The upper contact 16 is connected to a power supply rail connection 36 (e.g., VCC in FIG. 1a) by another via structure 38, from which programming and/or read current is selectively derived using the transistor 20.
The transistor 20 further includes a gate 24 and a second source/drain structure 26 connected to a column select line contact Cn using a via structure 40. The column line Cn is selectively used to conduct current from the power supply contact 36 through the cell material 12, the resistor plug 18, and the transistor 20 by connection to a power ground using one or more control transistors (not shown), by which the memory cell 10 and the state of the phase change material 12 may be programmed (e.g., written) and/or read. Such operations are performed on the cell 10 when the transistor 20 conducts between the source/drain regions 22 and 26, according to a signal at the gate 24. The gate 24 is controlled by row select logic (not shown) in the memory device 2, by which the cell 10 (e.g., and other cells in a logical row connected to the same row select logic signal) is operated on.
As illustrated in FIG. 1b, when a current 14, such as a programming current pulse, is applied to the cell 10, which passes through the resistive plug 18, heating of the phase change material 12 results near the interface between the material 12 and the plug 18 in a localized region 50 in the volume of material 12. One problem with the use of a single resistive plug 18 in the design of the memory cell 10 is the localized nature of the area or region 50 affected by the heating of the resistive plug 18. Although the plug 18 generates some amount of heat, the heating effect is somewhat inefficient because it is only localized to the bottom of the phase change material 12 in region 50.
It is noted in FIGS. 1a and 1b, that the volume of the affected phase change material in the region 50 determines how much resistivity difference results between the programmed and unprogrammed states (e.g., between the amorphous and crystalline states in a binary memory). Thus, it is desirable to impact a greater volume of phase change material by the heating (e.g., in region 50) to make it easier to differentiate between the binary states (e.g., or between any number of achievable states in a non-binary memory structure). For a given programming current level (e.g., or more generally for a given amount of applied energy), an improvement in the heat delivery over that provided by the single resistive plug 18 would allow a greater volume of phase change material 12 being programmed. Alternatively or in combination, less energy could be applied to achieve the same amount of affected material in the region 50. Thus, it is seen that a need exists for improving the energy transfer efficiency of phase change material memory cell programming operations.
It is also noted in FIGS. 1a and 1b that the structure of the conventional memory cell 10 has a further disadvantage. While a programming current 14 is applied to the cell 10, the underlying resistive plug 18 acts as a heat source to apply heat to the phase change material in the region 50. However, at the same time, the upper conductive contact 16 acts as a heat sink, drawing heat energy away from the phase change material 12. This is because the conductive contact 16 is highly conductive, both electrically and thermally (e.g., the contact 16 is typically fashioned from metal). Thus, in order to extend the affected region 50 upwards (e.g., to improve device reliability), it is necessary to apply even more energy via the current pulse 14. Consequently, there remains a need for improved phase change material memory cell structures and techniques for fabricating such memory devices, by which the above mentioned shortcomings associated with conventional devices can be mitigated or overcome.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The invention relates to memory cell devices and fabrication techniques where resistive plugs are formed above and below a phase change material to form a memory cell in a semiconductor memory device, by which the above mentioned and other difficulties can be mitigated or overcome. The plugs may be formed by implanting regions in high resistivity material above and below a phase change material layer to lower the resistivity in the implanted regions, and may be formed using a single implantation so as to facilitate alignment of the plugs with respect to one another.
One aspect of the invention involves semiconductor memory devices and memory cells therefore, comprising a volume of phase change material disposed in a semiconductor device with upper and lower surfaces, such as in the form of a film layer. The phase change material volume, which may be deposited using an electrically switchable chalcogenide alloy formed of antimony, tellurium, and germanium, for example, comprises a memory region extending between an upper portion of the upper surface and a lower portion of the lower surface. A first high resistivity material at least partially overlies the volume of phase change material, which has a first intermediate resistivity portion or plug contacting the memory region. In addition, a second high resistivity material at least partially underlies the volume of phase change material, with a second intermediate resistivity portion or plug contacting the memory region.
Phase change material in the memory region and the first and second intermediate resistivity portions form an electrical path for storage and retrieval of information in the memory cell. The heating effect of the upper and lower resistive plugs facilitates improved uniformity of heat transfer into the phase change material in the memory region, and hence may be employed to improve memory cell reliability, to improve the ability to differentiate between programmed states, and to reduce the amount of energy required to program the cell. Furthermore, the use of upper and lower resistive plugs mitigates the heat sink effect of prior designs where a conductive contact would draw programming energy away from the phase change material. In this respect, the invention further improves the thermal and electrical efficiency of programming operations associated with phase change material memory cells.
Conductive contact structures may be provided above the first (e.g., upper) intermediate resistivity portion or plug, as well as beneath the second resistive plug, such that application of a voltage across the first and second conductive contact structures causes a current to flow in the phase change material in the memory region and the first and second intermediate resistivity portions. One or both of the intermediate resistivity portions or plugs may comprise high resistivity material implanted with at least one of boron, arsenic, and phosphorus. In this way, the resistivity associated with the implanted portion(s) is less than that of the non-implanted high resistivity materials, creating a current channel or path. The upper and lower (e.g., first and second) intermediate resistivity plugs, moreover, may be aligned with one another along a vertical axis, so as to improve the efficiency and reliability of the cell.
Another aspect of the invention provides methodologies for fabricating a memory cell in a semiconductor memory device. The methods comprise depositing a first conductive contact layer over a substrate and depositing a first high resistivity layer over the first conductive contact layer, such as using undoped polysilicon or amorphous silicon. A volume of phase change material is deposited (e.g., such as a chalcogenide alloy formed of antimony, tellurium, and germanium, or the like) over the first high resistivity layer, which comprises a memory region in which a portion of the volume of phase change material extends between generally planar upper and lower surfaces of the volume of phase change material. The methodology further comprises depositing a second high resistivity layer over the volume of phase change material and depositing a second conductive contact layer over the second high resistivity layer.
In addition, the method comprises forming a first intermediate resistivity portion in the first high resistivity layer substantially beneath the memory region, and forming a second intermediate resistivity portion in the second high resistivity layer substantially above the memory region. The intermediate resistivity portions or plugs may be created by reducing first and second resistivities associated with the first and second intermediate resistivity portions of the first and second high resistivity layers, respectively, such as through implanting boron, arsenic, and/or phosphorus in the first and second intermediate resistivity portions using one or more implantation processes.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.